Fpga Implementation of Low Complexity Linear Periodically Time Varying Filter
نویسندگان
چکیده
This paper presents a low complexity architecture for a linear periodically time varying (LPTV) filter. This architecture is based on multi-input multi-output(MIMO) representation of LPTV filters. The input signal is divided into blocks and parallel processing is incorporated, there by considerably reducing the effective input sampling rate. A single multiplier can be shared for each linear time invariant (LTI) filter in the representation. Each LTI filter is realized in the transposed direct form filter using multiplier less multiplication structures based on Binary common bit patterns (BCS). The proposed structure is simulated, synthesized and implemented on Virtex v50efg256-7 Field Programmable Gate Array (FPGA).
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A Low complexity solution to the implementation of linear periodically time varying filters-FPGA implementation
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